The present invention relates to a high power voltage source converter in particular using series connection of forced turn off semiconductor elements.
Forced commutated high power converters have been realized with gate turn off thyristors (GTOs), gate-controlled thyristors (GCTs), and insulated gate bipolar transistors (IGBTs).
GTOs require strong snubber circuits limiting turn on dl/dt and turn off dV/dt of the semiconductor element. Additionally, GTOs exhibit quite a significant tolerance of control delay time. As a consequence, GTO series connection is difficult. It requires many bulky passive components and results in large converter switching loss.
GCT series connection so far also has been realized using snubber circuits. As a consequence, high efficiency has been achieved at low switching frequency, but applications requiring high switching frequency could not be addressed by such technology.
So far high voltage IGBTs have been the best choice. With a gate drive specially designed for IGBT series connection, the IGBT could be controlled to limit its anode voltage during operation and also to limit dl/dt during turn on. In such way passive power circuits such as snubbers and clamps were nearly omitted.
On the other hand the on-state loss of high voltage IGBTs is significantly higher than the on-state loss of comparable GCTs. With similar switching loss, GCTs therefore can show better performance in standard converter circuits. Moreover, GCTs are more powerful at reduced cost, and gate drive timing is more precise. Basically, GCTs therefore are favourite elements for high power converters.
Japanese Patent No. 3004774 proposes a snubber circuit, which can transfer the energy stored in the snubber capacitors into the reset circuit of anode reactors.
Japanese Patent Laid-open Publication No. Hei-05-111262 proposes a snubber and a zener diode connected in parallel to the anode-cathode terminals of a GTO.
Japanese Patent Laid-open Publication No. Hei-05-276650 connects a clamp in parallel to the drain source terminals of a FET. A chopper controls the clamp voltage.
U.S. Pat. No. 5,544,035 proposes snubber circuits connected in parallel to the anode-cathode terminals of GTOs. Dl/dt limiting reactors are located in alternating order with 2 GTOs. Each of these has a separate reset circuit.
U.S. Pat. No. 5,946,178 discloses different types of clamp circuit, which are connected to the collector-emitter or collector-gate terminals of the power semiconductor.
Japanese Pat. Laid-open Publication No. Hei-9-275674 discloses a clamp with chopper control, which is connected to the anode-cathode terminals of a power semiconductor (IGBT).
A building block for voltage source converters must be found which can handle highest power at elevated switching frequency with low power dissipation in the semiconductors and high converter efficiency. It must have a small number of active and passive power components in order to guarantee high converter reliability. The building block must include voltage clamping and dl/dt control. The building block must be suitable to realize 2 level converters 3 level converters and multilevel converters with and without series connection of such blocks.
In such a block the gate turn off semiconductors must be operated in snubberless clamped turn off mode. Dl/dt control during turn on must be realized by anode reactors. Reset circuits must be provided in parallel to such reactors. Clamp circuits must be arranged in such a way, that all clamping and voltage control tasks are realized by a single clamp per semiconductor switch.